{"id":3628,"date":"2018-06-25T18:16:36","date_gmt":"2018-06-25T09:16:36","guid":{"rendered":"https:\/\/www.waseda.jp\/fsci\/ict-robotics\/?p=3628"},"modified":"2023-02-22T18:26:11","modified_gmt":"2023-02-22T09:26:11","slug":"international-symposium-on-future-of-computer-technology-2018-isfct2018","status":"publish","type":"post","link":"https:\/\/www.waseda.jp\/fsci\/ict-robotics\/news-en\/3628","title":{"rendered":"International Symposium on Future of Computer Technology 2018 (ISFCT2018)"},"content":{"rendered":"
\n\n\n\n\n\n\n
Date<\/th>\n1:00PM-6:05PM July 24 (Fri.), 2018 (Reception opens at 12:30PM)<\/td>\n<\/tr>\n
Avenue<\/th>\nConference Room 102, Green Computing Systems Research and Development Center<\/td>\n<\/tr>\n
Participant fee<\/th>\nFree of charge *Pre-registration is required<\/td>\n<\/tr>\n
Organizer<\/th>\nFrontier of Embodiment Informatics: ICT and Robotics, Waseda University SGU program
\nAdvanced Multicore Processor Research Institute, Waseda University<\/td>\n<\/tr>\n
Sponsorship<\/th>\nIEEE Computer Society Japan Chapter
\nIEEE Computer Society Multicore STC
\nOscar Technology Corporation<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n

Message from Organizer, Prof. Hironori Kasahara<\/h3>\n

On July 24, 2018, in collaboration with the IEEE Computer Society (President: Prof. Hironori Kasahara of Waseda University), the Frontier of Embodiment Informatics: ICT and Robotics, Waseda University SGU program will hold the COMPSAC2018 conference at the Tokyo Hitotsubashi Hall and the National Institute of Informatics (NII). World-class researchers, winners of the IEEE Computer Society 2018 Computer Pioneer Award, Technical Achievement Award, and Distinguished Service Award, will be invited to COMPSAC to serve as the keynote speakers. Researchers will also be invited to the International Symposium on the Future of Computer Technology 2018: ISFCT 2018 being held at the Waseda Green Computing Research and Development Center on Tuesday, July 24.<\/p>\n

The world\u2019s most advanced symposium will be held with the following speakers.<\/p>\n

Attendance is free of charge, but pre-registration is required. We look forward to seeing you at the symposium.<\/p>\n

Program<\/h3>\n

Program<\/h4>\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
12:30<\/th>\nRegistration Start<\/td>\n<\/tr>\n
13:00 \u2013 13:10<\/th>\nOpening Address
\nProf. Shuji Hashimoto (Vice President of Waseda University)
\nProf. Hironori Kasahara (Waseda University \/ IEEE Computer Society President 2018 \/ ISFCT2018 Chair)<\/td>\n<\/tr>\n
13:10 \u2013 13:40<\/th>\nProf. Sorel Reisman
\n(California State University, Fullerton)<\/td>\n<\/tr>\n
13:40 \u2013 15:05<\/th>\nDr. Bjarne Stroustrup
\n(Morgan Stanley \/ Visiting Professor of Columbia University)<\/td>\n<\/tr>\n
15:05 \u2013 15:15<\/th>\nCoffee Break<\/td>\n<\/tr>\n
15:15 \u2013 16:05<\/th>\nProf. Margaret Martonosi
\n(Princeton University)<\/td>\n<\/tr>\n
16:05 \u2013 16:35<\/th>\nDr. Dejan Milojicic
\n(Hewlett Packard Labs)<\/td>\n<\/tr>\n
16:35 \u2013 16:45<\/th>\nCoffee Break<\/td>\n<\/tr>\n
16:45 \u2013 17:15<\/th>\nProf. Cecilia Metra
\n(University of Bologna)<\/td>\n<\/tr>\n
17:15 \u2013 17:35<\/th>\nProf. Hironori Kasahara
\n(Waseda University \/ IEEE Computer Society President 2018 \/ ISFCT2018 Chair)<\/td>\n<\/tr>\n
17:35 \u2013 17:55<\/th>\nDr. Christoph Schumacher
\n(Oscar Technology \/ Guest Assistant Professor of Waseda University)<\/td>\n<\/tr>\n
17:55 \u2013 18:05<\/th>\nClosing Address
\nProf. Shigeki Sugano (Waseda University \/ Leader of SGU Project: ICT and Robotics)<\/td>\n<\/tr>\n
18:05<\/th>\nClose<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n

Invited Speakers<\/h3>\n

\"\"<\/p>\n

Dr. Christoph Schumacher<\/p>\n

Waseda Visiting Researcher
\nOscar Technology<\/p>\n

Automatic parallelization for the embedded industry<\/h4>\n

Improvements in sequential software optimization are slowing down. As a result, software parallelization is becoming more and more popular to improve computing performance. Originating from academic high-performance computing projects, today, parallelization techniques can even augment performance of embedded applications such as gasoline engine management systems.<\/p>\n

This presentation introduces how the benefits of parallel execution can be transferred to industrial settings in the embedded domain. One challenge is to achieve both highest reliability and a high degree of analysis automation at the same time. Furthermore, integrating automatic parallelization into existing industry workflows requires a new class of tools and functionality. Finally, examples from real-world settings highlight how customers are enabled to overcome these issues by employing the OSCARTech\u00ae Compiler.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Christoph Schumacher is an application engineer at Oscar Technology Corporation, Tokyo. He also serves as Guest Assistant Professor at the Advanced Multicore Research Institute of Waseda University, Tokyo. In both of his roles, he takes on the challenge to apply automatic parallelization technology to real-world software.<\/p>\n

Christoph obtained a doctoral degree from RWTH Aachen University, Germany, in 2015, where he investigated the construction of parallel and distributed SystemC simulators. His current interests include processes and tools to lower the bar for the integration of automatic parallelization technologies.<\/p>\n

\"\"<\/p>\n

Prof. Sorel Reisman<\/p>\n

Professor, California State University, Fullerton
\nIEEE Computer Society President 2011
\nIEEE Computer Society E. Merwin for Distinguished service 2018 Winner<\/p>\n

MERLOT – The International Gateway for Finding Open Educational Resources<\/h4>\n

In an era of Open Educational Resources (OER), open source software (OSS), and Open Access (OA) publications, MERLOT, the Multimedia Educational Resource for Learning and Online Teaching, stands out as the longstanding, favored digital gateway for instructors seeking all manner of open resources for their teaching and research. The MERLOT community, which celebrated its 20th anniversary in 2017, consists of more than 150,000 registered members who have built a collection of almost 80,000 freely available, curated, multidisciplinary learning materials. With more than one million website visitors annually, MERLOT is the preferred international resource for discovering online teaching and learning materials. This presentation will discuss the concept of openness, including the use and reuse of learning objects, the new user interfaces and features in MERLOT (released in March, 2018), and will focus on MERLOT\u2019s \u2018Smart Search\u2019 integrated in 1) MERLOT own repository search, 2) direct search to more than a dozen popular digital libraries, and 3) pre-customized, profile-based WWW searches. There will be a focus on MERLOT\u2019s recently added discipline communities of Information Technology and Computer Science, endorsed by the IEEE Computer Society and the IEEE Education Society.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Sorel Reisman, recipient of the IEEE Computer Society 2018 Richard E. Merwin Award for Distinguished Service, is professor of information systems in the Department of Information Systems and Decision Sciences at California State University, Fullerton, Reisman is Managing Director of the international higher education, educational technology consortium, MERLOT (Multimedia Educational Resource for Learning and Online Teaching) at the California State University Office of the Chancellor.<\/p>\n

Reisman has presented\/published more than 120 articles including the books\u00a0Multimedia Computing: Preparing for the 21st Century, and Electronic Learning Communities \u2013 Current Issues and Best Practices.\u00a0 He continues to write and review articles and columns for\u00a0ITPro\u00a0and\u00a0Computer\u00a0magazines, and speaks internationally about his career-long passion on the use of technology for teaching computing.<\/p>\n

In 2011 Reisman established the IEEE-CS\u2019s Special Technical Communities (STCs) for which he received the IEEE-CS Outstanding Contribution Award.<\/p>\n

Reisman is Chair of the Standing Committee of the IEEE-CS signature COMPSAC conference, a Computer Society Golden Core member, member of Eta Kappa Nu, an elected member-at-large of the IEEE Publications, Services, and Products Board (PSPB), member of the\u00a0IEEE Xplore\u00a0Platform Guidance Committee, the IEEE Conference Publications Committee, and the Strategic Planning Committee of the IEEE Technical Activities Board.\u00a0 He has also been a member of the Education Activities Board, and was editor-in-chief of the IEEE eLearning Library.<\/p>\n

Reisman served as the IEEE-CS Vice President of Publications in 2008-2009, and IEEE-CS Vice President of Electronic Products and Services in 2006-2007. Prior to his executive committee positions, he chaired and served on many IEEE-CS committees as member-at-large of the IEEE-CS Publications Board, chair of the Magazines Operations Committee, founding member of the Computer Society Digital Library (CSDL) Committee, and chair of the Web Development Committee.\u00a0 He was an editorial board member of\u00a0IEEE Software\u00a0magazine, a founding editorial board member of\u00a0IEEE Multimedia magazine, and\u00a0IEEE IT Professional\u00a0on which he is currently Advisory Board Chair.<\/p>\n

Reisman received his EE degree, MA, and PhD in Computer Applications from the University of Toronto and was appointed a Fulbright Specialist in 2014.<\/p>\n

\"\"Dr. Bjarne Stroustrup<\/p>\n

Managing Director, Morgan Stanley
\nVisiting Professor, Columbia University
\nC++ Developer
\nIEEE Computer Society Computer Pioneer Award 2018 Winner<\/p>\n

Using Modern C++ – stepping up to C++17<\/h4>\n

The C++17 ISO standard has just become official and is already shipping from the major compiler suppliers (GCC, Clang, Microsoft). The shape of C++20 is under active discussion and early versions of some potential new features are already available.<\/p>\n

This talk will consider the implications for the use of C++. It will offerl guidelines and techniques for using new and older features with focus on features that can make a significant difference to developers by simplifying programming or increasing performance.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Stroustrup is the designer and original implementer of C++ as well as the author of The C++ Programming Language (Fourth Edition) and A Tour of C++, Programming: Principles and Practice using C++ (Second Edition), and many popular and academic publications. Dr. Stroustrup is a Managing Director in the technology division of Morgan Stanley in New York City as well as a visiting professor at Columbia University. He is a member of the US National Academy of Engineering, and an IEEE, ACM, and CHM fellow. He is the recipient of the 2018 NAE Charles Stark Draper Prize for Engineering and the 2017 IET Faraday Medal. He did much of his most important work in Bell Labs. His research interests include distributed systems, design, programming techniques, software development tools, and programming languages. To make C++ a stable and up-to-date base for real-world software development, he has been a leading figure with the ISO C++ standards effort for more than 25 years. He holds a master\u2019s in Mathematics from Aarhus University and a PhD in Computer Science from Cambridge University, where he is an honorary fellow of Churchill College.<\/p>\n

\"\"Prof. Margaret Martonosi<\/p>\n

Professor, Princeton University
\nResearcher in low-power computing
\nIEEE Computer Society Technical Achievement Award 2018 Winner<\/p>\n

New Metrics and Models for a Post-ISA Era: Managing complexity and scaling performance in Heterogeneous Parallelism and Internet-of-Things<\/h4>\n

Pushed by both application and technology trends, today\u2019s computer systems employ unprecedented levels of heterogeneity, parallelism, and complexity as they seek to extend performance scaling and support new application domains. From datacenters to Internet-of-Things devices, these scaling gains come at the expense of degraded hardware-software abstraction layers, increased complexity at the hardware-software interface, and increased challenges for software reliability, interoperability, and performance portability This talk will explore how new metrics, models, and analysis techniques can be effective in this \u201cPost-ISA\u201d era of shifting abstractions. The talk will cover hardware and software design opportunities, methods for formal verification, and a look into the implications on technologies like IoT.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Margaret Martonosi is the Hugh Trumbull Adams \u201935 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She is also Director of Princeton University\u2019s Keller Center for Innovation in Engineering Education. Martonosi\u2019s research interests are in computer architecture and mobile computing. Her work has included the development of the Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on hardware-software interface approaches to manage heterogeneous parallelism and power-performance tradeoffs in systems ranging from smartphones to chip multiprocessors to large-scale data centers. Martonosi is a Fellow of both IEEE and ACM. Notable awards include the 2018 IEEE Technical Achievement Award, the 2010 Princeton University Graduate Mentoring Award, and the 2013 Anita Borg Institute Technical Leadership Award. Her research has earned four recent Test-of-Time Paper Awards: the 2015 ISCA Long-Term Influential Paper Award, 2017 ACM SIGMOBILE Test-of-Time Award, 2017 ACM SenSys Test-of-Time Paper award, and 2018 (Inaugural) HPCA Test-of-Time Paper award.<\/p>\n

\"\"Dr. Dejan S. Milojicic<\/p>\n

Senior Researcher and Managing Director of HP Labs,
\nIEEE Division VIII Director, IEEE Computer Society President 2014<\/p>\n

Generalize or Die: Operating Systems Support for Memristor-based Accelerators<\/h4>\n

The deceleration of transistor feature size scaling has motivated growing adoption of specialized accelerators implemented as GPUs, FPGAs, ASICs, and more recently new types of computing such as neuromorphic, bio-inspired, ultra low energy, reversible, stochastic, optical, quantum, combinations, and others unforeseen. There is a tension between specialization and generalization, with the current state trending to master slave models where accelerators (slaves) are instructed by a general purpose system (master) running an Operating System (OS). Traditionally, an OS is a layer between hardware and applications and its primary function is to manage hardware resources and provide a common abstraction to applications. Does this function, however, apply to new types of computing paradigms?<\/p>\n

This talk revisits OS functionality for memristor-based accelerators. We explore one accelerator implementation, the Dot Product Engine (DPE), for a select pattern of applications in machine learning, imaging, and scientific computing and a small set of use cases. We explore typical OS functionality, such as reconfiguration, partitioning, security, virtualization, and programming. We also explore new types of functionality, such as precision and trustworthiness of reconfiguration. We claim that making an accelerator, such as the DPE, more general will result in broader adoption and better utilization.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Dejan is a distinguished technologist at Hewlett Packard Labs, Palo Alto, CA [1998-]. His areas of technical expertise include operating systems, distributed systems, and systems management. He worked in the OSF Research Institute, Cambridge, MA [1994-1998] and Institute \u201cMihajlo Pupin\u201d, Belgrade, Serbia [1983-1991]. He received his PhD from University of Kaiserslautern, Germany (1993); and MSc\/BSc from Belgrade University, Serbia (1983\/86). Dejan was a managing director of the Open Cirrus Cloud Computing testbed (2007-2011), with the academic and industrial sites in US (6), Europe (3), and Asia (6). Dejan has published over 180 papers and 2 books; he has 25 granted patents and over 50 patent applications. Dejan is an IEEE Fellow (2010), ACM Distinguished Engineer (2008), and USENIX member. He was president of IEEE Computer Society and is currently on IEEE Board. He has been on many conference program committees and journal editorial boards. He started two conferences (IEEE ASAP; USENIX WIESS).<\/p>\n

\"\"Prof. Cecilia Metra<\/p>\n

Professor, University of Bologna, IEEE Computer Society President-Elect 2018 (President 2019)<\/p>\n

Reliability Challenges for High Performance Electronics in the Internet of Things Era<\/h4>\n

The continuous advances of microelectronic technology is enabling an increasingly widespread and pervasive use of electronics in our lives. The possibility to connect electronic circuits and systems to each other through the Internet, and to exchange information among them, thus constituting the Internet of Things \u2013 IoT, is paving the way to applications and features that were simply unthinkable a few years ago. However, the increased electronic systems\u2019 complexity and performance offered by the advances in microelectronic technology, as well as their possible communication and cooperation in the IoT framework, comes together with their increased vulnerability to environmentally induced faults and ageing mechanisms occurring in the field, which pose continuously new challenges to their reliability. These reliability challenges, as well as possible solutions to face them, will be addressed in this talk.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Cecilia Metra is a full professor at the University of Bologna, Italy, where she has worked since 1991, and from which she received a PhD in electronic engineering and computer science. In 2002, she was visiting faculty consultant for Intel Corporation.<\/p>\n

She is the President-Elect of the IEEE Computer Society (CS) 2018 and President 2019. She has been a member of the IEEE Computer Society Board of Governors since 2013, and of the IEEE Council on Electronic Design Automation Board of Governors since 2015. She was 2017 vice president of CS Member and Geographic Activities, and served as CS Secretary in 2015 and Vice President for Technical and Conference Activities in 2014. She is the Editor in Chief of the IEEE Transactions on Emerging Topics in Computing (2018-2020) and she was Editor in Chief of Computing Now (2013-2016) and Associate Editor in Chief of IEEE Transactions on Computers (2007-2012). She is on the IEEE The Institute Advisory Board as well as on editorial boards of several journals, including IEEE Design&Test, Journal of Electronic Testing, and Design Automation for Embedded Systems.<\/p>\n

She served as first vice chair of the Test Technology Technical Council (TTTC), chair of the TTTC Educational Program, and chair of the TTTC Communication Group. She contributed to numerous IEEE international conferences\/symposia \/workshops as general\/program chair\/co-chair (14 times), vice-general\/program chair\/co-chair (6 times), topic\/track chair (34 times), and technical program committee member (91 times).<\/p>\n

She has published extensively (185+ papers) on design for test and reliability of integrated circuits and systems. Her research has received public and private funding (from companies such as Intel Corporation, STMicroelectronics, etc.) at national and international levels. Her involvement with industry was also recognized by a joint patent with Philips Research.<\/p>\n

Cecilia Metra is an IEEE Fellow, IEEE CS Golden Core Member, and a member of the IEEE Honor Society IEEE-HKN. She has received two Meritorious Service Awards and five Certificates of Appreciation from the IEEE CS.<\/p>\n

\"\"<\/p>\n

Prof. Hironori Kasahara<\/p>\n

Professor, Waseda University
\nJapan\u2019s first IEEE Computer Society President (2018)
\nParallel Compiler Multicore Researcher
\nIEEE Computer Society President 2018<\/p>\n

OSCAR Compiler for Automatic Multigrain Parallelization, Memory Optimization and Power Reduction for Multicore Systems<\/h4>\n

To improve processing performance and reduce power consumption, multicore processors have been widely used in embedded systems like a smartphone, self-driving cars, and IoT to high-performance systems like cloud servers and supercomputers. However, to realize efficient parallel processing of a target application program, parallelization of the program and memory usage optimization require long time periods and large cost. This talk introduces OSCAR (Optimally SCheduled Advanced MultiprocessoR) compiler allows users to have efficiently parallelized and memory optimized parallel programs for various multicores available in the market automatically in a short time and low cost. This short talk includes technical demos by the OSCAR compiler that gives us scalable performance improvement and power reduction for:<\/p>\n

\u30fbscientific applications like earthquake simulation and 3D FFT,
\n\u30fbmedical applications like heavy particle cancer therapy and capsule inner cameras,
\n\u30fbindustry applications like automotive hard-realtime engine control and MATLAB\/Simulink model based designed programs, and
\n\u30fbsoft-realtime multimedia programs like H.264 and Optical flow<\/p>\n

on various homogeneous and heterogeneous multicores from Intel, IBM, Fujitsu, ARM, Infineon, and Renesas multicore processors.<\/p>\n

Click here for the slide<\/a><\/p>\n

Biography<\/h4>\n

Hironori Kasahara is an IEEE Computer Society President 2018 and a professor in the Department of Computer Science and Engineering at Waseda University. He is an IEEE Fellow, an IPSJ Fellow, a Golden Core Member of the IEEE Computer Society, a professional member of the IEEE Eta Kappa Nu, a member of the Engineering Academy of Japan and the Science Council of Japan. He received a PhD in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at University of California, Berkeley, and the University of Illinois at Urbana\u2013Champaign\u2019s Center for Supercomputing R&D.<\/p>\n

He has served as a chair or member of 250 society and government committees, including a member of the CS Board of Governors and Executive Committee; chair of CS Planning Committee, Constitution & Bylaws Committee, Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, and ASPLOS; board member of IEEE Tokyo section; and member of the Earth Simulator and K supercomputer committees. Kasahara received the CS Golden Core Member Award, IFAC World Congress Young Author Prize, Sakai Special Research Award, and the Japanese Minister\u2019s Science and Technology Prize. He led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 215 papers, 155 invited talks, and 42 international patents. His research has appeared in 557 newspaper and Web articles.<\/p>\n

\n

Sponsors<\/h3>\n
\n\n\n\n
Organizer<\/th>\nFrontier of Embodiment Informatics: ICT and Robotics, Waseda University SGU program
\nAdvanced Multicore Processor Research Institute, Waseda University<\/td>\n<\/tr>\n
Sponsorship<\/th>\nIEEE Computer Society Japan Chapter
\nIEEE Computer Society Multicore STC
\nOscar Technology Corporation<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n
\n

Venue<\/h3>\n

Green Computing Systems Research<\/a> Organization<\/a>
\n27 Waseda-machi, Shinjuku-ku, Tokyo, Japan 162-0042
\nTEL:+81-(0)3-3203-4369<\/p>\n