{"id":147,"date":"2018-10-17T00:27:15","date_gmt":"2018-10-16T15:27:15","guid":{"rendered":"http:\/\/www.sgu-ictrobotics.sci.waseda.ac.jp\/wp\/?p=147"},"modified":"2022-12-20T17:58:30","modified_gmt":"2022-12-20T08:58:30","slug":"181017_joseptorrellas","status":"publish","type":"post","link":"https:\/\/www.waseda.jp\/fsci\/ict-robotics\/news\/147","title":{"rendered":"10\u670819\u65e5\u3000\u30a4\u30ea\u30ce\u30a4\u5927\u5b66\u30a2\u30fc\u30d0\u30ca\u30fb\u30b7\u30e3\u30f3\u30da\u30fc\u30f3\u3000Prof. Josep Torrellas\u3000\u8b1b\u6f14\u4f1a\u306e\u304a\u77e5\u3089\u305b"},"content":{"rendered":"
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\u30bf\u30a4\u30c8\u30eb<\/th>\nExtreme Energy-Efficient Computer Architectures<\/td>\n<\/tr>\n
\u5834 \u6240<\/th>\n\u65e9\u7a32\u7530\u5927\u5b6640\u53f7\u9928102\u5ba4\uff08\u30b0\u30ea\u30fc\u30f3\u30fb\u30b3\u30f3\u30d4\u30e5\u30fc\u30c6\u30a3\u30f3\u30b0\u30fb\u30b7\u30b9\u30c6\u30e0\u7814\u7a76\u6a5f\u69cb\uff09 \uff08\u5730\u56f3<\/a>\uff09<\/td>\n<\/tr>\n
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\u5f8c \u63f4<\/th>\nIEEE Eta Kappa Nu Waseda University Student Chapter Mu Tau
\nIEEE Multicore STC<\/td>\n<\/tr>\n<\/tbody>\n<\/table><\/div>\n
\n

Extreme Energy-Efficient Computer Architectures<\/h3>\n

Energy and power are the main constraints in computer architecture today and in the foreseable future. Unfortunately, there is no silver-bullet technique that can single-handedly solve the problem. Instead, we need to apply a set of technologies that, in combination, can improve energy efficiency substantially. This talk presents some of these technologies. Cores need to be designed to flexibly operate at a wide range of voltages, and techniques such as power gating and voltage speculation need to be widespread. New formal controllers can manage multiple parameters concurrently for minimal resource waste. Further, if novel devices can be integrated with conventional CMOS, highly efficient architectures can be designed.<\/p>\n

\"\"

Prof. Josep Torrellas<\/p><\/div>\n<\/div>\n

\n

 <\/p>\n

\n

\u30d7\u30ed\u30d5\u30a3\u30fc\u30eb<\/h3>\n

Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign (UIUC). He leads the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He has been the director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He is a Fellow of IEEE, ACM, and AAAS. He received the 2015 IEEE CS Technical Achievement Award, and the 2017 UIUC Campus Award for Excellence in Graduate Student Mentoring.<\/p>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

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