{"id":2054,"date":"2015-09-08T15:37:47","date_gmt":"2015-09-08T06:37:47","guid":{"rendered":"http:\/\/www.waseda.jp\/fsci\/gips\/?p=2054"},"modified":"2015-09-20T17:25:26","modified_gmt":"2015-09-20T08:25:26","slug":"inoue-yasuaki","status":"publish","type":"post","link":"https:\/\/www.waseda.jp\/fsci\/gips\/other-en\/2015\/09\/08\/2054\/","title":{"rendered":"Professor INOUE Yasuaki"},"content":{"rendered":"
Introduction<\/h5>\n

\"04-2\"<\/a><\/p>\n

Dr. of Engineering (Waseda University)
\nPractical experience in the development of analog LSI’s and design technologies at Sanyo Semiconductor Company. No likes and dislikes in human beings (as well as wines).
\nHP\uff1ahttp:\/\/www.f.waseda.jp\/inoue_yasuaki\/<\/a><\/p>\n

E-Mail\uff1a
\n\"inoue\"<\/a>
\n<\/a><\/p>\n

Research<\/h5>\n

\"04ch\"<\/a>Circuit-Level Verification Technologies<\/span><\/strong><\/p>\n

It is a difficult challenge, an engineer’s dream, in high performance system LSI developments to finish designs with the first silicon without repeating any more design modifications again. The circuit-level verification technologies are to verify the validity of LSI designs at the circuit level by using numerical techniques solving nonlinear circuit equations. The technologies are very important not only for analog designs but also for digital. We try to realize the dream by proposing new and efficient verification approaches, algorithms and circuit models.
\nKey words: circuit-level verification, nonlinear circuit analysis, circuit simulation, analog LSI design technology, analog LSI CAD<\/div>\n

 <\/p>\n

Research Area<\/h5>\n
    \n
  • Circuit-Level Verification Technologies<\/li>\n
  • Numerical Analysis of Nonlinear Circuits and Systems<\/li>\n
  • Analog LSI Designs<\/li>\n
  • LSI Simulation Technologies<\/li>\n<\/ul>\n

     <\/p>\n","protected":false},"excerpt":{"rendered":"

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