Takeshi Ikenaga was born in Kitakyushu city, Japan on July 8, 1964. He received B.E. and M.E. degrees in electrical engineering from Waseda University, Tokyo, Japan, in 1988, and 1990, respectively, where he belonged to the Information Systems Laboratory directed by Professor Katsuhiko Shirai (past president of Waseda University). He also received Ph.D degree in information & computer science from Waseda university in March 2001.
He joined LSI Laboratories, Nippon Telegraph and Telephone Corporation (NTT) in 1990, where he has been undertaking research on the design and test methodologies for high-performance ASICs, a real-time MPEG2 encoder chip set, and a highly parallel LSI & system design for image-understanding processing.
 
From 1999 to 2000, he was a visiting researcher at the Architecture & Language Implementation (ALI) Group (directed by Professor Charles C. Weems) of the Department of Computer Science, University of Massachusetts, Amherst, USA. In 2002, he returned to Kitakyushu city and worked for the Kitakyushu Foundation for the Advancement of Industry, Science andTechnology (FAIS) as an invited researcher.
He is presently a professor in the system LSI field of the Graduate School of Information, Production and Systems, the Graduate School of Fundamental Science and Engineering, and Department of Electronic and Photonic Systems, School of Fundamental Science and Engineering (FY2006-2013), Waseda University.
His current research interests are application SoCs for image and video processing, which covers video compression (e.g. H.264/AVC, H.264/SVC, H.265/HEVC), video filter (e.g. super resolution, noise reduction), video recognition (e.g. feature point detection, object tracking) and video communication (e.g. UWB, LDPC, public key encryption). He also has interests in application-oriented many-core processor design. He is promoting many national projects, such as Program for Leading Graduate Schools, Global COE, Core Research for Evolutional Science and Technology (CREST), Special Coordination Funds for Promoting Science and Technology, Knowledge Cluster project and Grants-in-Aid for Scientiic Research. He is also promoting industry academia collaborations with many companies.
 
  Past R&D Activities  
 
MPEG2 encoder chip set and board (1995)
- the first MPEG2 PC board in the world -
 
 
Real-time image processing LSI & board with
256-by-256 processing elements (1999)
- the world largest highly-parallel CAM LSI with 1M bit -
 
  Selected Publications  
 
  • Z. Liu, T. Ikenaga, et al.,  "Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 21, No. 5, pp. 601-610, May 2011.
  • Z. Liu, T. Ikenaga, et al., "Motion Estimation Optimization for H.264/AVC Using Source Image Edge Features", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 19, No. 8, pp. 1095-1107, Aug. 2009.
  • Z. Liu, T. Ikenaga, et al., "HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis", IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, pp 594-608, Feb. 2009
  • Z. Liu, T. Ikenaga, et al., "Motion Feature and Hadamard Coefficient based Fast Multiple Reference Frame Motion Estimation for H.264", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 18, No. 5, pp.620-632, May 2008.
  • T. Ikenaga and T. Ogura, "Real-time Morphology Processing using Highly-parallel 2D Cellular Automata CAM2," IEEE Trans. on Image Processing, Vol. 9, No. 12, Dec. 2000.
  • T. Ikenaga and T. Ogura, "A Fully-parallel 1Mb CAM LSI for Real-time Pixel-parallel Image Processing," IEEE Journal of Solid-State Circuit, Vol. 35, No. 4, April 2000
  • T. Ikenaga and T. Ogura, "CAM2: A Highly-parallel Two-dimensional Cellular Automaton Architecture," IEEE Trans. on Computers, Vol. 47, No. 7, July 1998
  • T. Ikenaga and T. Ogura, "A DTCNN Universal Machine based on Highly-parallel 2D Cellular Automata CAM2," IEEE Trans. on Circuits and Systems I, Vol. 45, No. 5, May 1998

    Ph.D Dissertation: "Highly-parallel Two-dimensional Cellular Automaton Architecture and its Application to Real-time Image Processing" (pdf 1,236k)

    -> Researcher Database

    -> Research Profiles

    -> Scopus

 
  Professional activities and Awards  
 
  Dr. Ikenaga is a senior member of the Institute of Electrical and Electronics Engineers (IEEE), a member of the Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ) and a board member of the Institute of Image Electronics Engineers of Japan (IIEEJ). He served as an associate editor and a secretary of the IEICE Transactions (incl. special sections) and a secretary of the system LSI technology commitee of the Japan Electronics and Information Technology Industries Association (JEITA). He also served as an organizing committee or a technical program committee members for many international conferences (e.g. ASP-DAC, IEEE ISCAS, IEEE MWSCAS, IEEE SiPS, ICFPT, ISPACS, ASSCC, IEEE ICME, SISA, ASICON,  APSIPA ASC, VLSI-DAT and APCCAS) and a chair of Signal processing systems TC for Asia-Pacific Signal and Information Processing Association (APSIPA) .

He received the Furukawa Sansui award from Waseda University in 1988. In 1992, he also received the IEICE Research Encouragement Award for his paper ``A Test Pattern Generation for Arithmetic Execution Units''. His team also awarded at the DAC/ISSCC 2006 student design contest (Conceputual 1st place), the 8th and 9th LSI IP design award (IP prize) in 2006 and 2007, the 10th LSI IP design award (IP excellent prize) in 2008, Excellent paper award from IIEEJ in 2008, CSPA best paper, ISOCC Samsun award in 2009, ICD best poster award in 2010, IMPS best poster award in 2011, and so on.

 
 
  Education  
 
To @learn system LSI technologies, it is highly desired to design actual LSI chips with various CAD tools and evaluate them from various technical points of view. To attain the purpose, I teach classes named "System LSI design" . I also teach "Video signal processing" and "Microprocessor".
 
 
System LSI Laboratory where the class is held.
 

Pipeline processor LSI that we designed at 2003-2006 Spring semester's class

* VDEC Rohm 0.35um 5 mm x 5 mm

* 16 bit 5 stage pipeline processor x 8 - 12

 


 

Pipeline processor LSI that we designed at 2007 Spring semester's class

* VDEC Rohm 0.18um 2.5 mm x 2.5 mm

* 16 bit 5 stage pipeline processor x 10

   
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